Intel terascale

Intel belives threads are the answer to parallel/distributed computing. That's a good market strategy for the moment, but it is not the final solution to a real parallel computing. Every program written in a OO or structural programming follows an imperative paradigm. It makes simple and easy the creation of sequential sets of instructions. Threads are the easiest way to introduce parallelism into such a paradigm, but they are not simple to manage: critical sections and side effects make the programs flow difficult to design and debug and often are at the base of inefficiencies and errors.
Functional programming languages makes the parallelism easy and fully exploitable, but they are not good to project large software platforms .... how to solve this problem?
Today we have the technology to spatially (i.e. in parallel) execute small functional graphs (or circuits) automatically generated from sequential set if instructions. Look at this paper. This could be the final solution to
the parallel computing dilemma: "parallel formalism"-"difficult programming" or "easy programming"-"sequential formalism".

... For the moment look at the terascale tech from Intel.

"Intel Labs has created an experimental “Single-chip Cloud Computer,” a research microprocessor containing the most Intel Architecture cores ever integrated on silicon CPU chip – 48 cores. It incorporates technologies intended to scale multi-core processors to 100 cores and beyond, such as an on-chip network, advanced power management technologies and support for “message-passing.” Architecturally, the chip resembles a cloud of computers integrated into silicon."

• Scalable multi-core architectures which integrate streamlined processor cores and accelerators using a fast, energy-efficient, modular core-to-core infrastructure.
  Examples: 80-core prototype, Tera-scale Emulator, Dynamic Thermal Management, Task Queues .
  
• Memory sharing and stacking to provide a high bandwidth, flexible, cache & memory hierarchy which supports many simultaneous threads fairly and efficiently.
  Examples: 3D Stacking, Cache Quality of Service.
  
• High Bandwidth I/O and Communications which balance the compute demands with I/O and network demands within the platform power and cost budgets.
  Examples: High-speed Copper I/O, Silicon Photonics, I/O Accelerators.